1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a semiconductor device having a diffusion layer, and to a method for manufacturing such a semiconductor device.
2. Background Art
In recent years, concurrent to the miniaturization and higher integration of semiconductor devices, the necessity of forming a plurality of transistors in a semiconductor device has arisen. However, if the number of transistors is simply increased, power consumption increases. Therefore, the voltage impressed to each transistor must be lowered. Furthermore, in order not to lower the switching speed even if the impressed voltage is lowered, the gate length of each transistor must be reduced.
In a transistor having a short gate length, however, the roll-off phenomenon of threshold voltage is significant. Therefore, as a countermeasure to the roll-off phenomenon, the junction of diffusion layer (source-drain and extensions) has been shallowed. For example, for CMOS transistors of 65-nm-technology node, the target values of the gate length of 32 nm and the depth of the diffusion layer of 10 to 17 nm have been presented in ITRS (the International Technology Roadmap for Semiconductors).
As a method for forming such an extremely shallow junction, the use of SPE (solid phase epitaxy) for pMOS has been proposed. In nMOS, arsenic (As) implanted into a diffusion layer can be activated at a temperature as low as about 600° C. However, boron (B) implanted into the diffusion layer of pMOS cannot be activated at such a temperature. Therefore, in order to realize the shallow junction of diffusion layers at a low temperature, a shallow junction by SPE is used especially in pMOS. The shallow junction by SPE is realized using the following method.
First, a gate insulating film and a gate electrode are formed on a substrate having an element isolating region, wells, and the like formed thereon. Thereafter, germanium (Ge) ions or silicon (Si) ions are implanted using the gate electrode as mask to form an amorphous layer on the surface of the substrate. Then, ions such as B are implanted to form an extension. Furthermore, a sidewall is formed, and ions such as B are implanted again to form a source and a drain. Thereafter, heat treatment at about 600° C. is performed to recrystallize to locate B on the lattice locations. Thereby, B is activated.
In this method for forming a shallow junction, ions such as Ge are previously implanted before implanting B ions to form an amorphous layer. Thereby, the implanting energy when B ions are implanted can be controlled to some extent to reduce the flying range of the B ions, and channeling by implanted ions when the extension is formed can be prevented.
On the other hand, when B ions are implanted, the substrate is damaged to some extent. The defect caused by this damage results in the occurrence of a leak current. Therefore, the damage must be restored. In order to restore the damage, recrystallization by annealing at above a certain high temperature is required. However, annealing at a high temperature extends and deepens the junction, and shallow junction cannot be realized. Therefore, especially in a semiconductor device that requires extremely shallow junction, priority is given to the realization of shallow junction using low-temperature annealing at about 600° C., or short time annealing.
Here, the target value of leak current presented by ITRS for a semiconductor device for LSTP (low stand-by power) having a long gate length and requiring no shallow junctions is 1 pA/μm. On the other hand, the target value of leak current for a semiconductor device for LOP (low operating power) requiring shallow junctions is 700 pA/μm to allow leak current to some extent.
With the current demands for multi-function semiconductor devices, a system LSI wherein transistors for LOP and transistors for LSTP are formed in a chip may be required; for example, the memory is composed of transistors for LSTP that require little standby power, and the peripheral circuits are composed of transistors for LOP that has a high speed and require little power consumption. In such a case, diffusion layers of different junction depth must be formed in a chip. Specifically, the formation of transistors having deep junctions to some extent and requiring high-temperature heat treatment for inhibiting leak current is required on one hand, and the formation of transistors that cannot be subjected to high-temperature heat treatment for realizing extremely shallow junctions is required on the other hand.